The invention relates to a method of manufacturing an integrated circuit. The integrated circuit comprises a semiconductor body which is provided at a surface with a multilayer electrode system. The system of electrodes has at least three layers, which are referred to hereinafter as the first, second and third electrode layers. The electrode layers are successively provided on the semiconductor body, and are separated from each other by insulating layers.
A contact is formed between the third electrode layer and a region which forms part of the integrated circuit. The region of the integrated circuit is defined already before the first electrode layer is provided. This region is covered with a dielectric layer which extends above the region and beyond the edges of the region above the surface of the semiconductor body. A contact window is defined in the dielectric layer for the contact.
The first and second electrode layers may consist, for example, of polycrystalline silicon. The third electrode layer may consist of a pattern of Al. If desired, the polycrystalline silicon may then be further converted into a silicide by alloying it with a suitable material.
The insulating layers between the electrode layers may consist of silicon oxide obtained by oxidation of the polycrystalline silicon.
Suitable materials other than polycrystalline silicon, such as for example Mo or Al, may alternatively be used for the first and second electrode layers.
The region which is contacted by the third electrode layer may be a diffused zone in the semiconductor body. However, in many cases this region will consist of a part of an electrode layer which is provided before (under) the first electrode layer. Such a contact region may be, for example, a gate electrode of an insulated gate field effect device, such as a field effect transistor or a charge coupled device.
Due to the tendency to increasingly reduce the lateral dimensions of integrated circuits, the step of providing the contact window in the dielectric layer, mostly an oxide layer, is very critical. When no additional measures are taken, it often occurs that due to misalignment or due to an excessively long etching treatment, not only the oxide above the region to be contacted, but also oxide beside this region is removed. As a result, a short circuit is produced when the Al contact is provided.
In certain cases, for example when the region to be contacted has a width of about 4 .mu.m and the contact window also has a width of about 4 .mu.m, it is practically impossible to manufacture useable circuits with a reasonable yield due to the misalignment problem without taking additional measures. In general, it is not possible to provide a contact when the region to be contacted is smaller than the sum of the smallest contact hole on the mask, the underetching distance and the alignment tolerance.
When the region to be contacted consists of an underlying polysilicon or metal layer, the problem described above can be avoided by using a so-called etching barrier in the form of a silicon nitride layer under the polysilicon or metal. The silicon nitride then extends beyond the edges of the region to be contacted. Such a method is described, inter alia, in U.S. Pat. No. 4,306,353. A disadvantage of this known method is that it usually requires a change in the process of making the circuit. This known method will usually require the production of an additional nitride layer. As a result, the process, which is already complicated, will comprise even more steps.